As future generations of electronic devices advance in complexity and decrease in size, a growing need exists for a dielectric material more effective than SiO2. Increased demands on ultra-large scale integrated (ULSI) circuits have required that the SiO2 that forms the gate oxide of field-effect transistors be made laterally smaller and, consequently, thinner. Eventually, however, the SiO2 layers will be required to be so small and thin that electron tunneling will make current leakage unacceptably high for low-power devices.
Hafnium oxide (HfO2), also known as hafnia, has been identified as a promising candidate to replace SiO2 as a gate dielectric. Hafnium oxide, having a relatively high bulk dielectric constant (k=15–25), would allow gate oxides to be physically thicker (for a given capacitance), which could significantly reduce tunneling. Hafnium oxide also exhibits a large band gap (approximately 5.7 eV) and a band offset (greater than 1 eV) with substrates such as silicon. Further, the diffusion of hafnium atoms into substrates such as silicon, particularly during or after post-deposition anneals, has proven to be negligible.
However, when sufficiently thick, an amorphous hafnium oxide film tends to crystallize at relatively low temperatures (approximately 400° C.) to form monoclinic, cubic, and/or tetragonal crystallites. Polycrystalline hafnium oxide facilitates unwanted metal or impurity diffusion through grain boundaries and degrades gate stack performance. Polycrystalline hafnium oxide also causes higher leakage current because of charge transport through grain boundaries. Further, the surface of polycrystalline hafnium oxide may have grains with different terminations associated with different surface potentials due to different dipole strength and orientation of the terminations. Such varied surface potentials could be detrimental to device yield if the variation of the surface potential is sufficiently large and the grain sizes are comparable to gate dimensions.
Accordingly, it is desirable to provide a semiconductor structure and a method for fabricating a semiconductor structure without the undesirable drawbacks described above. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.